1. Field of the Invention:
This invention relates to a MOS-type semiconductor integrated circuit device, and more particularly to an integrated circuit device incorporating MOS transistors formed in a vertical configuration.
2. Description of the Prior Art:
In recent years, the packing density of integrated circuits (hereinafter referred to as IC) incorporating MOS transistors has been steadily increasing. To achieve a higher-density integration of such ICs, MOS transistors incorporated therein have been miniaturized into submicron regions. The basic circuit of digital ICs is usually an inverter circuit, which is constituted by MOS transistors. As the miniaturization of such MOS transistors progresses, various disadvantageous phenomena occur as follows. First, as the gate sizes of the MOS transistors are reduced, a punchthrough occurs between the source and drain regions. This is caused by a so-called short-channel effect. Thus, a leakage current between the source and drain regions can hardly by suppressed. As a result, a standby current of the inverter circuit increases. Second, the miniaturization of MOS transistors causes the internal electric fields thereof to be stronger. Thus, the threshold values and mutual conductances of the MOS transistors fluctuate depending on a so-called hot-carrier effect. As a result, the characteristics of the MOS transistors are deteriorated. This deteriorates the characteristics of the inverter circuit, i.e., both the operating speed and operating margin thereof are reduced. Third, when the gate lengths of MOS transistors are reduced to achieve the miniaturization thereof, the reductions of gate widths inevitably are limited so as to securely maintain a prescribed current-carrying capacity. As a result, it is difficult to sufficiently reduce the inverter circuit area. For example, in the configuration of a DRAM (dynamic random access memory), the miniaturization of memory cells, per se, is significantly progressing. However, the peripheral circuit of such memory cells, which is about 40% of the entire chip area, cannot be sufficiently miniaturized because of the above-described gate size restriction. This prevents the miniaturization of the total DRAM chip size.
Further, when a gate electrode region is made of a polysilicon film, the CR time constant is constituted by a polysilicon film resistance and a gate capacitance. This CR time constant causes a delay in gate signal transmission. As the miniaturization of an MOS transistor progresses, a gate oxide film becomes thinner, and a gate capacitance increases. Thus, the CR time constant also increases. As a result, the delay in gate signal transmission dominates the switching time of the inverter circuit. Moreover, the contact capacitance between source and drain regions also increases along with the miniaturization of the device. As a result, the switching speed of the inverter circuit is decreased.
As described above, in the conventional technique of manufacturing MOS ICs, it is difficult to suppress the leakage current of the MOS inverter circuits. Further, the above-described hot carrier effect causes the reliability of the circuits to be lowered. Moreover, the circuit area cannot be sufficiently reduced because of the requirements to maintain a prescribed current-carrying capacity. In addition, the gate widths of the circuits must be small to reduce the signal delay at the gate electrodes of the circuits. These disadvantages exist not only in the MOS inverter circuits, but also in the MOS flip-flop circuit configuration.